The last inch of copper: why AI's next decade is a power problem, not a transistor problem
Two thousand amps at 0.85 volts is the actual engineering problem the industry is spending hundreds of billions to solve. Here's the plain-English map of who's building what.
Curiously Optimistic: an issue on AI compute architecture and the power-efficiency race
By Bob Girton, August Grace Advisory
In short
The next decade of AI won't be won on transistors. It'll be won on electricity, and specifically on the brutal problem of shoving roughly 2,000 amps at less than one volt into a chip the size of a saltine, thousands of times per building, without cooking the building.
A few things worth holding onto:
The binding constraint on AI infrastructure through about 2032 is power delivery, not chip density.
The whole power path, from grid to building to rack to card to package to silicon, is being redesigned at once. That is what the AI capex cycle is actually funding.
The economics are shifting from training (steady, miles per gallon) to inference (spiky, cost per answer), and that shift is what drives the power arms race.
The winners after Nvidia are mostly unglamorous power and capacitor names most investors have never heard of.
And this is an optimistic story. The bottleneck is well understood, the physics isn't exotic, and it's being funded with real money right now.
Why AI's real bottleneck is power, not transistors
Most of the AI infrastructure story still gets told as a compute story. Bigger models, more chips, more data centers, more money. It's a good story. It's also, increasingly, the wrong one.
Talk to the people actually designing the next generation of AI hardware, though, and they’re not really arguing about chips anymore. They’re arguing about electricity. Specifically, how to get enormous amounts of it into a piece of silicon the size of your thumbnail, hundreds of thousands of times per building, without setting the building on fire.
That is not a metaphor. That is the actual, physical problem the industry is spending hundreds of billions of dollars to solve.
I want to walk through what’s happening in plain terms, because it’s one of the most consequential redesigns of computing since the shift from CPUs to GPUs, and it’s mostly invisible from the outside. If you take one thing away, take this: the interesting question is no longer how many transistors you can fit on a chip. It’s how many watts you can shove into the chip, and how quickly you can turn those watts on and off. Everything downstream, model size, inference cost, capex, follows from that.
How much power does a single AI GPU actually use?
Start here. Your home has an electrical service that delivers somewhere between 100 and 200 amps of current at 240 volts. That’s enough to run your fridge, your oven, your HVAC, and everything else, all at once. It’s roughly 24 to 48 kilowatts of capacity.
A single Nvidia Vera Rubin GPU, which starts shipping in volume in late 2026, is designed to draw about 1,800 watts. Not 1.8 kilowatts across your whole house. 1.8 kilowatts into one chip the size of a large postage stamp.
Now here’s the twist. The chip doesn’t run at 240 volts. Or 120. Or 12. It runs at about 0.85 volts. Less than a AA battery.
There's one equation you need, and then you're set for the rest of this piece: power equals voltage times current. That's it. That's the whole toolkit. If you keep the power fixed (1,800 watts) and shrink the voltage way down (to 0.85 volts), the current has to shoot up to compensate.
So how much current is that?
Roughly 2,000 amps arriving at a single chip.
That is ten times the current running through your entire house, delivered into a piece of silicon smaller than a saltine cracker. And a single AI rack has hundreds of these chips. A single data center hall has thousands.
That is the actual engineering problem. Everything else in AI hardware right now is a consequence of it.
Why is high current the enemy? The water hose analogy
Here’s an analogy that will get you the whole rest of the way through this.
Imagine you need to deliver a fixed amount of water to a fire. You have two choices. You can use a skinny hose at very high pressure, or you can use a giant fat hose at low pressure. Either one gets the water there. But the fat, low-pressure hose is enormously more expensive, because you have to build a much bigger hose, use much more material, and deal with much more friction and heat as the water sloshes through.
Electricity works the same way. Voltage is the pressure. Current is the flow. High voltage plus low current is easy to move around a building efficiently. Low voltage plus high current is a nightmare. It requires thick copper, it wastes energy as heat, and every foot of wire between the source and the destination bleeds off power.
And crucially: the losses in the wire go up with the square of the current. Double the current, quadruple the loss. This is not a small effect. This is why every high-power system ever built, from the national electrical grid to your car’s alternator, has always tried to move energy at the highest voltage it can manage and step it down at the last possible moment.
Now imagine trying to run a fire hose at zero pressure. That’s roughly what’s happening at the AI chip. The chip demands 2,000 amps at less than one volt. You have to get those 2,000 amps to arrive at exactly the right instant, at exactly the right voltage, without wasting the equivalent of a small hotel’s worth of energy along the way.
The way the industry is solving this is by redesigning every layer of the power path at once. Every layer. From the electrical grid outside the building all the way to the last inch of copper between a voltage regulator and the chip. That is what the AI capex cycle is actually funding.
The power path, from grid to chip, in plain English
Let me walk you through the ladder. Six layers. Skip the details if you like; the pattern is the same at every layer.
Layer 1: Grid to building. From AC to DC.
For twenty years, data centers took high-voltage AC power from the utility, stepped it down to 415 or 480 volts AC, and distributed AC around the building. Every server rack then had its own box that converted AC to DC. Every one of those conversions loses energy and generates heat, like every time you change money at an airport kiosk, you lose a little in the spread.
Nvidia has now announced, and multiple ecosystem partners are building around, a new architecture that takes utility power and immediately converts it once to 800 volts DC at the perimeter of the building. Then it distributes that 800-volt DC power straight into the racks. No more AC in the building. No more four or five conversion steps.
The results, per Nvidia and independent analysts:
Up to four conversion steps eliminated
End-to-end efficiency up more than 5%, which at gigawatt scale is dozens of megawatts recaptured
Copper use down roughly 45%, because higher voltage means lower current means thinner wires
Total infrastructure cost down roughly 30%
Nvidia has publicly partnered with a company called Navitas on the specialty power chips that make this possible. Vertiv is building the power modules. Foxconn is building an entire 40-megawatt data center in Taiwan around it. CoreWeave, Oracle, and Lambda are already designing to it. This is not a research paper. This is happening now, with money.
Analogy: Instead of every apartment in a skyscraper having its own currency exchange for foreign visitors, you put one exchange at the front door of the building and hand everyone US dollars from there.
Layer 2: The rack. From 40 kilowatts to a megawatt.
A rack is a metal cabinet about the size of a large refrigerator. It holds servers.
Five years ago, a rack full of general-purpose servers drew maybe 10 to 15 kilowatts of power, roughly the same as a couple of electric ovens running at once. An early AI rack running Nvidia’s H100 chips drew about 40 kilowatts. The current generation, Blackwell GB200, draws 120 to 130 kilowatts per rack. That’s the same as a small factory.
The next generation, Nvidia’s Rubin Ultra Kyber rack, which is targeted for 2027, is designed to draw 600 kilowatts to 1 megawatt. Per rack. That’s the electrical draw of about 500 homes, concentrated into a single cabinet.
Analogy: Imagine the electrical demand of an entire suburban cul-de-sac being served through a single garden hose. That’s the pressure the rack designers are dealing with.
Layer 3: Inside the rack. Moving power to each server.
Historically, the power inside a rack ran at 12 volts. A few years ago, the industry shifted to 54 volts because the current was becoming unmanageable. The next step, being designed now, moves the internal rack voltage to 400 volts, and eventually 800 volts DC. Same voltage as the whole building.
Same reasoning as before. The higher you keep the voltage, the less current you have to push through the copper busbars, and the less energy you waste as heat.
Layer 4: The server card. Getting power to the chip.
This is where the engineering starts to look less like wiring and more like sculpture.
The voltage regulators, the little boxes that do the final conversion from 12 volts down to 0.85 volts for the chip, used to sit next to the chip on the same circuit board. Current flowed sideways across the board to reach the chip. That worked fine when the currents were 50 or 100 amps.
At 2,000 amps, it doesn’t work at all. The board can’t carry that much sideways current without wasting huge amounts of energy in the copper.
So the industry is moving to something called vertical power delivery. The voltage regulators move to the back of the circuit board, sitting directly underneath the chip, and inject current straight up through the board into the silicon. The path shrinks from inches to millimeters.
The companies doing this work were sleepy specialty names five years ago and are central to the AI story now: Infineon, which showed its latest generation at a conference in early 2025, along with Empower Semiconductor, Vicor, and Monolithic Power Systems.
Analogy: instead of a food-court kitchen wheeling meals to tables on a cart across the room, every table gets a dumbwaiter that lifts the food straight up from a kitchen directly below.
Layer 5: The chip package. Reservoirs of energy.
Even with perfect power delivery, there’s still a problem. AI chips don’t draw power steadily. They gulp it. The load can swing from near-zero to 2,000 amps in about a millionth of a second. If the voltage regulator can’t keep up, the chip crashes.
To handle that, the industry uses capacitors: essentially tiny electrical shock absorbers, or, better, tiny batteries that can release energy in microseconds. Every AI chip is surrounded by thousands of them. The numbers are worth sitting with.
A Vera Rubin rack contains about 600,000 capacitors. Per rack.
AMD’s competing MI450 chip went through a late design change in which a single small capacitor part number jumped from 1,440 pieces per board to 10,544 pieces per board. That’s a 632% increase, because the design needed more shock absorption.
Panasonic’s own investor materials from late 2024 disclosed that AI servers use 22 to 30 times more capacitors than general-purpose servers.
The industry is now moving capacitors off the circuit board and onto the chip package itself, to get them closer to the die. Samsung’s electronics arm announced a $993 million contract with an undisclosed US hyperscaler for specialty on-package silicon capacitors, with deliveries scheduled from 2027 through 2028. That is a real, boring, sub-industry most investors have never heard of, and it is about to be very lucrative.
Analogy: think of a Costco loading dock. If you’re moving pallets steadily all day, one forklift is fine. But if a truck shows up unannounced and has to be unloaded in ninety seconds, you need twenty forklifts standing by right at the dock. Capacitors are the standby forklifts, and AI chips need thousands of them within arm’s reach.
Layer 6: The chip itself. Regulators moving onto the silicon.
The endgame is to eliminate the last inch of copper entirely by building the voltage regulator directly into the same piece of silicon as the compute chip. Intel has demonstrated this on production nodes. TSMC has published a roadmap for combining voltage regulation and capacitors directly into the chip package in the 2028 to 2030 window.
If that lands as planned, the whole power-delivery problem gets absorbed into the chip itself, and the industry moves on to the next constraint, which is probably cooling.
Training vs. inference: why AI's economics are shifting to cost per answer
This is where the physics turns into an economic story worth caring about. AI hardware does two very different things. It trains models, the big, expensive, one-time process of teaching a system by grinding through mountains of data. And it runs them, which the industry calls inference, the part where you ask a chatbot a question and get an answer back. Training is what got AI to where it is. Inference is where the industry is going to make its money.
These two workloads have very different power profiles. Training is steady: you run flat-out for weeks, and the metric that matters is how much computing you get per watt of electricity, roughly like miles per gallon on a cross-country drive. Inference is spiky: millions of users asking questions at unpredictable moments, each request short, latency everything. The metric that matters there is cost per answer, or in the industry’s language, watts per token (a token is roughly a word).
For the last few years the whole industry optimized for training. That is changing fast. Nvidia’s language around the new Rubin chip has quietly shifted toward inference economics, with claims of ten times the throughput per megawatt versus Blackwell on inference workloads. Ten times is not incremental. It is a step change in what it costs to run a large model in production.
And that shift is exactly what drives the power-delivery arms race. Inference wants many smaller chips, running at lower voltages, packed closer together, drawing more current per square inch of silicon. That is precisely the recipe behind the 2,000-amps-at-0.85-volts problem this piece opened with. The economic pressure and the physical pressure point in the same direction, and both push hard.
Who wins the AI power buildout beyond Nvidia?
This is where the curiously-optimistic framing earns its keep, so bear with me while I get slightly evangelical. The innovation in this cycle is genuinely spread across dozens of companies working on completely different pieces of the same problem. This is not an Nvidia monoculture. It is closer to a symphony that Nvidia happens to be conducting. Here is my working map of who is doing what.
Nvidia designs the whole system and sets the reference; it tells everyone else what the target looks like. AMD is a genuine number-two on the chip itself and is pushing the same physics from a different direction. Broadcom, Marvell, and Alchip design custom AI chips for the hyperscalers (Google, Meta, Amazon, Microsoft), and every one of those chips has to solve the same power problem. TSMC does the advanced packaging that makes on-chip capacitors and, eventually, integrated regulators possible; it is the quiet linchpin of the whole story.
One layer out, Infineon, Empower Semiconductor, Vicor, and Monolithic Power build the power-delivery modules that sit inches from the chip. Navitas, Wolfspeed, Transphorm, and EPC build a newer class of power semiconductor made of gallium nitride and silicon carbide, which switches faster and handles higher voltage than traditional silicon; that is the enabling chemistry for the 800-volt building. Panasonic, Murata, TDK, Samsung Electro-Mechanics, and KEMET/YAGEO build the capacitors, all 600,000 of them per rack: boring, high-volume, and now a real dollar market. Vertiv, Eaton, Schneider, and the specialty HVDC-gear makers build the power infrastructure of the buildings themselves.
And the hyperscalers, meaning CoreWeave, Lambda, Oracle Cloud, and Together AI, plus Google, Meta, Amazon, and Microsoft, are now inside the reference-design conversation as co-architects. That is genuinely new. Data-center operators used to just buy servers. Now they help design the racks and the buildings.
Dozens of teams, different chemistries, different physics, different markets, all pointing at the same problem. That kind of setup, historically, tends to solve the problem, not on any one team’s schedule, but on a collective schedule that is usually short by historical standards.
What I take away as an investor and operator
Three things. First, the binding constraint on AI infrastructure for the next five to seven years is power delivery, not transistors. Chipmakers are still shrinking transistors, but per-chip power draw is climbing faster than transistor efficiency is improving, and that gap gets closed at the package, the card, the rack, and the building. If you want to know who wins the AI capex cycle after Nvidia, look at the companies whose products live on that closure path. Many of them are unglamorous, most are not household names, and some are worth serious money.
Second, the shift from training-first to inference-first economics changes which architectural moves matter and which financial metrics to track. Watts per token and cost per answer are the numbers that will dominate AI earnings calls three years from now. Anything that improves the efficiency of running a model, as opposed to training one, will get rewarded: better power delivery, but also better memory architectures, better cache management, better decoding. If you are evaluating an AI-infrastructure investment, look at its inference story, not just its training benchmarks.
Third, and most important, this is fundamentally an optimistic story. The industry is not stuck. The bottleneck is well understood, the physics is not exotic, the roadmap is credible, and it is being funded with real money right now by the biggest and most sophisticated companies in the world. When that many well-capitalized teams converge on a physical problem with an obvious return on investment, the problem tends to get solved. Not perfectly, and not on time, but faster than almost anyone outside the industry expects.
If the last decade of AI was about proving the algorithms scale, the next decade is about proving the electricity does. That is a far more tractable problem than it looks, and it is where I would spend my attention.
Curiously Optimistic is a newsletter about specialty chemicals, advanced materials, industrial operations, and AI, written from the operator’s line. If a friend or colleague forwarded this to you, you can subscribe at the top of the page. If you want to talk about anything in this piece, my calendar is open.
Bob Girton is the principal at August Grace Advisory, where he leads investment and strategic advisory work in chemicals, advanced materials, and AI infrastructure.
Sources and further reading
NVIDIA 800V HVDC Architecture Will Power the Next Generation of AI Factories, NVIDIA Technical Blog
NVIDIA 800V HVDC Deep Dive: From 54V Racks to Megawatt AI Factories, SanYi
NVIDIA, Partners Drive Next-Gen Efficient Gigawatt AI Factories, NVIDIA Blog
NVIDIA Rubin Platform Begins H2 2026 Ramp, Let’s Data Science
NVIDIA Selects Navitas for 800V HVDC Architecture, Yahoo Finance / GlobeNewswire
NVIDIA AI Server Power Roadmap: Kyber’s Next Generation Strategy, Ming-Chi Kuo / Medium
The New Power Stack for AI Servers, SemiVision
Conductive Polymer Capacitor Market and Design-In Guide to 2035, passive-components.eu
NVIDIA Rubin Platform, Open Models, Autonomous Driving, NVIDIA Blog